Compensation of phase lock loop (pll) phase distribution caused by power amplifier ramping

ABSTRACT

Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.

RELATED APPLICATIONS

This Application is a Divisional Application of co-pending applicationSer. No. 12/483,708, which was filed on Jun. 12, 2009. The entirecontents of application Ser. No. 12/483,708 are hereby incorporatedherein by reference.

BACKGROUND

Digitally controlled oscillators (DCOs) are commonly employed in avariety of applications, including communication and timing circuitry.In particular, DCOs are commonly used in phase-locked loop (PLL)systems. Functionally, a DCO may be viewed as a circuit that seeks totransform an input control voltage signal to an output voltage signalhaving a desired frequency.

In this case, the output signal of the PLL is normally compared againsta reference signal, and a loop filter is used to tune the DCO in amanner dependent upon the comparison such that the output signal“matches” the reference signal. Such PLLs are usually used to synthesizesignals at a desired frequency or, for example, to recover a clocksignal from a data stream. PLLs can also be advantageously used inmobile radio for the purposes of signal modulation.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is described with reference to the accompanyingfigures. In the figures, the left-most digit(s) of a reference numberidentifies the figure in which the reference number first appears. Theuse of the same reference numbers in different figures indicates similaror identical items.

FIG. 1 is a block diagram of a digital type II phase lock-loop.

FIG. 2 is a block diagram of a digital type I phase lock-loop.

FIG. 3 is a block diagram of a phase lock-loop comprising adifferentiator module.

FIG. 4 is a block diagram of the differentiator module of FIG. 3.

FIG. 5 is a timing diagram of the phase lock-loop of FIG. 3.

FIG. 6 is a flowchart employing the system of FIG. 3.

FIG. 7 is a block diagram of a digital loop filter of the digital type Iphase lock-loop of FIG. 2.

FIG. 8 is a block diagram of a transceiver module of the phase lock-loopcomprising a differentiator module of FIG. 3.

DETAILED DESCRIPTION

The present application describes compensation of phase disturbances ofa phase lock-loop during power ramp up or down of a power amplifier. Thephase lock loops may be employed in wireless communication devices. Manyspecific details are set forth in the following description and in FIGS.1-8 to provide a thorough understanding of various implementations. Oneskilled in the art will understand, however, that the subject matterdescribed herein may have additional implementations, or that theconcepts set forth may be practiced without several of the detailsdescribed in the following description. More specifically, a system isdescribed that is able to switch between type I and type II PLL modesdepending on the power state of the power amplifier without introducingadditional disturbances.

Digital Type II Phase Lock Loop

FIG. 1 shows an overview of a digital type II phase lock loop (PLL) 100.PLL 100 comprises a time to digital converter (TDC) module 102, adigital loop filter module 104, an integrator module 106, a digitalcontrolled oscillator (DCO) module 108, a first divider module 110, asecond divider module 112, a power amplifier (PA) module 114, asigma-delta module 116, and a target frequency module 118. PLL 100generates an output signal, via DCO module 108, that is proportional toa reference signal or within a desired frequency band of a referencesignal depending upon the application desired, described further below.

DCO module 108 is configured to receive a control signal S₁ fromintegrator module 106 and generate an output signal S₂. Output signal S₂is controlled by, and has parameters dependent upon, control signal S₁.More specifically, altering control signal S₁ alters output signal S₂.Thus, to obtain a desired output signal S₂, control signal S₁ isaltered.

First divider module 110 is configured to receive output signal S₂ fromDCO module 108 and reduce the frequency of output signal S₂ by a divisorto produce a divided signal S₃. The first divider module 110 is furtherconfigured to receive a signal S_(divisor) that is output from targetfrequency module 118 via sigma-delta module 116. Signal S_(divsor)contains information regarding the divisor that divider module 110employs to reduce the frequency of output signal S₂. The magnitude ofthe divisor is determined by the application desired.

TDC module 102 is configured to receive divided signal S₃ from dividermodule 110 and further configured to receive a reference signal S₄.Reference signal S₄ may be any type of signal dependent upon theapplication desired. TDC module 102 determines a phase error betweendivided signal S₃ and reference signal S₄ (i.e. a relative phasedifference between divided signal S₃ and reference signal S₄). TDCmodule 102 outputs this as comparison signal S₅.

Digital loop filter module 104 is configured to receive signal S₅ fromTDC module 102. Digital loop filter module 104 is a low pass filter andthus limits the bandwidth of signal S₅ and outputs this as signal S₆.Integrator module 106 is configured to receive signal S₆ from digitalloop filter module 104. Integrator module 106 accumulates the phaseerror within signal S₆ and outputs this as control signal S₁. Asmentioned above, altering of control signal S₁ alters output signal S₂.Output signal S₂ is altered to have a frequency that is proportional toreference signal S₄ as dependent upon the application desired.

Second divider module 112 is configured to receive output signal S₂ fromDCO module 108 and reduce the frequency of output signal S₂ by a divisorto produce a second divided signal S₇. The magnitude of the divisor isdetermined by the application desired. PA module 114 is configured toreceive second divided signal S₇ and amplify signal S₇ and output thisas amplified signal S₈.

Type II PLL 100 offers many advantages as compared to other types ofphase lock-loops, i.e., improved noise suppression of DCO module 108.However, PA module 114 may generate an undesirable feedback signal S₉that is input to and picked up by DCO module 108 and that comprises aharmonic with the same frequency of output signal S₂ that is output byDCO module 110. Signal S₉ may introduce a phase transient within PLL 100when a power of PA module 114 is ramping up or down, which isundesirable. To that end, a digital type I phase lock loop hascharacteristics that may be desirable during power ramp or down of PAmodule 114, as described further below.

Digital Type I Phase Lock Loop

FIG. 2 shows an overview of digital type I PLL 200. Portions of PLL 200are analogous to portions of PLL 100 mentioned above with respect toFIG. 1. More specifically, a TDC module 202, a digital loop filtermodule 204, a DCO module 208, a first divider module 210, a seconddivider module 212, a PA module 214, a sigma-delta module 216, and atarget frequency module 218 are analogous to TDC module 102, digitalloop filter module 104, DCO module 108, first divider module 110, seconddivider module 112, PA module 114, sigma-delta module 116, and targetfrequency module 118, respectively, of FIG. 1. As such, any reference toany portion of the analogous portions of PLL 100 may be appliedanalogous to the corresponding portion of PLL 200. However, PLL 200differs slightly from PLL 100. More specifically, DCO module 208 isconfigured to receive signal S₆ that is output from digital loop filtermodule 204, i.e. signal S₆ and signal S₁ are substantially the same.

Type I PLL 200 offers some advantages as compared to other types ofphase lock loops, i.e., improved linearity when employed as an inbandphase modulator. Further, PLL 200 permits static phase deviations of DCOmodule 208. Since the phase error is not integrated in PLL 200, aconstant phase error leads to a differing value of control signal S₁.Further, as a result of feedback signal S₉ from PA module 214 modifyingthe tuning characteristics of DCO module 208 by adding a frequencyoffset which is proportional to the power of feedback signal S₉, thephase error is also proportional to the power of feedback signal S₉. Incontrast, the phase error is integrated in type II PLL 100 and thus iscontrolled towards zero. However, in comparison with PLL 100, PLL 200has drawbacks in noise suppression of DCO module 208. Furthermore, PLL200 may have phase drifts due to self-heating on the chip of PLL 200,all of which is undesirable.

It may therefore be desirable to employ PLL 200 (type I PLL) duringpower ramp or down of PA module 114 and employ PLL 100 when power issubstantially constant for PA module 114, i.e combining the phasetransient behaviors of both type I PLL and type II PLL. Thus, duringpower ramp up or down of PA module 114, the phase error will beapproximately proportional to the power of PA module 114 but will notchange upon the power of PA module 114 being substantially constant.Further, when the power has become substantially constant for PA module114, the benefits of PLL 100 (type II PLL) are realized such as improvednoise suppression of DCO module 108.

Combining Phase Transient Behavior of Digital Type I Phase Lock Loopswith Digital Type II Phase Lock Loops

FIG. 3 shows an overview of a system 300 that employs the benefits ofPLL 200 (type I PLL) during power ramp or down of PA module 114 andemploys the benefits of PLL 100 (type II PLL) when power has becomesubstantially constant for PA module 114. Further, system 300 is able toswitch between the type I PLL mode and the type II PLL mode withoutgenerating phase transients in system 300 that may violate the phaseerror specification of system 300.

System 300 comprises a time to digital converter (TDC) module 302, adigital loop filter module 304, an integrator module 306, a digitalcontrolled oscillator (DCO) 308, a first divider module 310, a seconddivider module 312, a power amplifier (PA) 314, a sigma-delta module316, a target frequency module 318, and a differentiator module 320.

Switching to PLL type I

Upon power ramp up or down of PA module 114, it may be desired to switchsystem 300 to PLL type I mode. In PLL type I mode, feedback signal S₉ isminimized, if not prevented, within system 300.

DCO module 308 is configured to receive a control signal S_(1′) fromintegrator module 306 and generate an output signal S_(2′). Outputsignal S_(2′) is controlled by, and parameters thereof dependent, oncontrol signal S_(1′). More specifically, altering of control signalS_(1′) alters output signal S_(2′). Thus, to obtain a desired outputsignal S_(2′), control signal S_(1′) is altered.

First divider module 310 is configured to receive output signal S_(2′)from DOC module 308 and reduce the frequency of output signal S_(2′) bya divisor to produce a divided signal S_(3′). First divider module 110is further configured to receive a signal S_(divisor′) that is outputfrom target frequency module 318 via sigma-delta module 316. SignalS_(divsor) contains information regarding the divisor that dividermodule 310 employs to reduce the frequency of output signal S_(2′). Themagnitude of the divisor is determined by the application desired.

TDC module 302 is configured to receive divided signal S_(3′) fromdivider module 310 and further configured to receive a reference signalS_(4′). Reference signal S_(4′) may be any type of signal dependent uponthe application desired. TDC module 302 determines a phase error betweendivided signal S_(3′) and reference signal S_(4′) (i.e. a relative phasedifference between divided signal S_(3′) and reference signal S_(4′)).TDC module 302 outputs this as comparison signal S_(5′).

Digital loop filter module 304 is configured to receive signal S_(5′)from TDC module 302. Digital loop filter module 304 is a low pass filterand thus limits the bandwidth of signal S_(5′) and outputs this assignal S_(6′). Differentiator module 320 is enabled such that it isconfigured to receive signal S_(6′) from digital loop filter module 304.

FIG. 4 shows differentiator module 320 in further detail. Differentiatormodule 320 comprises a flip-flop 400 and an adder/subtractor 402. In afurther implementation, differentiator module 320 comprises a pluralityflip-flops depending upon the application desired. Flip-flop 400 isimplemented as a D flip-flop, which is commonly known in the art, havinga clock input 404, an output 406, and an enable input 408. Enable input408 is configured to receive a signal S_(10′). To that end, when signalS_(10′) is set to logical high, differential module 320 is enabled. Thedata input D of flip-flop 400 is configured to receive signal S_(6′) andoutput a signal S_(11′). Adder/subtractor 402 is configured to receivesignal S_(11′) from flip-flop 400 and further configured to receivesignal S_(6′) from digital loop filter 304. Adder/subtractor 402determines a difference of signal S_(11′) and S_(6′) and outputs this assignal S_(12′). Further, as a result of signal S_(6′) being constant inthe locked state, output signal S_(12′) of differentiator module 316will remain at zero.

Integrator module 306 is configured to receive signal S_(12′) fromdifferentiator module 320. Integrator module 306 accumulates the phaseerror within signal S_(12′) and outputs this as signal S_(1′). Asmentioned above, altering of control signal S_(1′) alters output signalS_(2′). Output signal S_(2′) is altered to have a frequency that isproportional to reference signal S_(4′) depending on the applicationdesired. Furthermore, as a result of signal S_(12′) output fromdifferentiator module 316 remaining at zero, signal S_(1′) does notchange. To that end, as a result of differentiator module 316 beingenabled, integrator module 306 is not active from the point of view ofsystem 300. Thus, system 300 does not see/recognize any step duringswitching, as long as switching is done when the PLL phase error issettled.

Returning to FIG. 3, second divider module 312 is configured to receiveoutput signal S_(2′) from DCO module 308 and reduce the frequency ofoutput signal S_(2′) by a divisor to produce a second divided signalS_(7′). The magnitude of the divisor is determined by the applicationdesired. PA module 314 is configured to receive second divided signalS_(7′) and amplify signal S_(7′) and output this as amplified signalS_(8′).

When differentiator module 320 is enabled, system 300 is in type I PLLmode and thus power ramp or down of PA module 314 may start. Duringpower ramp or down of PA module 314, tuning characteristics of DCOmodule 308 are modified, i.e. a frequency offset proportional tofeedback signal S_(9′) is added to control signal S_(1′). As a result ofsystem 300 maintaining the frequency of output signal S_(2′), system 300compensates for the added frequency offset of feedback signal S_(9′).Thus, signal S_(1′) will be controlled such that the frequency of outputsignal S_(2′) remains substantially constant and signal S_(1′) willapproximately follow the amplitude of feedback signal S_(9′)proportionally. Moreover, due to the PLL digital phase error processingin Type I mode has a constant and finite gain for constant phase errors,the phase error will also be proportional to the amplitude of feedbacksignal S_(9′).

Switching to PLL type II

Upon the power of PA module 314 becoming substantially constant, it maybe desired to switch system 300 to PLL type II mode. To switch system300 to PLL type II mode, flip-flop 400 of differentiator module 320 isfrozen. More specifically, enable signal S_(10′) input to enable input408 is set to zero. Thus, the value of flip-flop 400 withindifferentiator module 320 is set to hold and differentiator module 320subtracts the last active value of signal S_(12′) from signal S_(6′).Thus, system 300 is in PLL type II mode as differentiator module 316 isno longer “cancelling” integrator module 308. Signal S_(6′) output fromdigital loop filter 304 stays at the actual level while signal S_(12′)input to integrator module 308 is zero. Thus, differentiator module 316has been “bypassed” without generating a phase transient within system300.

Transceiver Module Associated with PA Module 314

In a further implementation, FIG. 8 shows system 300 comprising atransceiver module 122, with PA module 114 being associated withtransceiver module 122. Transceiver module 122 is configured to receivesignal S_(7′). As a result, PLL 300 is switchable between type I modeand type II mode depending upon the power state of transceiver module122 (i.e ramping or substantially constant), analogous to that abovewith respect to PA module 114.

PLL 200 with Switchable Digital Loop Filter

Referring back to FIG. 2, in a further implementation, a transferfunction of digital loop filter module 204 may be switchable to enablechanging of a behavior of PLL 200, i.e. between type I mode and type IImode. FIG. 7 shows digital loop filter module 204 in more detail. Morespecifically, a transfer function of digital loop filter module 204 isswitchable between a low pass filter with integrating behavior (pole ats=0) and a low pass filter without integrating behavior depending uponthe power state of the power amplifier. When the power state of PAmodule 214 becomes substantially constant, the integral loop factor ofdigital loop filter module 204 is not zero and the transfer function ofdigital loop filter module 204 is switched to a low pass filter withintegrating behavior and thus PLL 200 is in type II mode. When the powerstate of PA module 214 is ramping up or down, the integral loop factorof digital loop filter module 204 is zero and the transfer function ofdigital loop filter module 204 is switched to a low pass filter withoutintegrating behavior and thus PLL 200 is in type I mode. As a result,PLL 200 is switchable between type I mode and type II mode dependingupon the power state of PA module 214.

PLL 100 with Switchable Direct Connection

Referring back to FIG. 1, in a further implementation, integrator module106 may be switchable such that integrator module 106 may be bypassedwithin PLL 100 depending on the power state of PA 114. Morespecifically, when the power state of PA module 114 becomessubstantially constant, integrator module 106 is not bypassed and iscoupled to DCO module 108, as described above, and thus PLL 100 is intype II mode. When the power state of PA module 114 is ramping up ordown, integrator module 106 is bypassed such that digital loop filtermodule 104 is coupled to DCO module 108, i.e. DCO module 108 isconfigured to receive signal S₆ from digital loop filter module 104(signal S₆ and signal S₁ are substantially the same), and thus PLL 100is in type I mode. As a result, PLL 210 is switchable between type Imode and type II mode depending upon the power state of PA module 114.

Timing Diagram of System 300

FIG. 5 shows a timing diagram 500 of the switching of system 300 betweentype I PLL mode and type II PLL mode. Timing diagram has 5 differingtime regions 502, 504, 506, 508, and 510 of the state of the power of PAmodule 314.

During time region 502, the power of PA module 314 is substantiallyconstant. Thus system 300 is in PLL type II mode and enable signalS_(10′) is set to zero.

During time region 504, the power of PA module 314 is ramping up. Thussystem 300 is in PLL type I mode and enable signal S_(10′) is set tological high.

During time region 506, the power of PA module 314 is substantiallyconstant. Thus system 300 is in PLL type II mode and enable signalS_(10′) is set to zero.

During time region 508, the power of PA module 314 is ramping down. Thussystem 300 is in PLL type I mode and enable signal S_(10′) is set tological high.

During time region 510, the power of PA module 314 is substantiallyconstant. Thus system 300 is in PLL type II mode and enable signalS_(10′) is set to zero.

Further, timing diagram 500 shows output signal S₂ of PLL 100 and outputsignal S_(2′) of system 300 versus the power state of PA module 314. Asis evident, a phase transient is introduced in PLL 100 after power rampup or down while system 300 operates without any disturbances.

Process Model 600

FIG. 6 shows a method 600 of employing system 300. The process 600 isillustrated as a collection of referenced acts arranged in a logicalflow graph, which represent a sequence that can be implemented inhardware, software, or a combination thereof. The order in which theacts are described is not intended to be construed as a limitation, andany number of the described acts can be combined in other orders and/orin parallel to implement the process.

At step 602, a power state of PA module 314 is determined. The powerstate being either ramping up/down or constant.

At step 604, if the power of PA module 314 is constant, enable signalS_(10′) is set to zero that is input to differentiator module 316. Thus,differentiator module 316 is not enabled.

At step 606, system 300 is in type II PLL mode.

At step 608, if the power of PA module 314 is ramping up/down, enablesignal S_(10′) is set to logical high that is input to differentiatormodule 316. Thus, differentiator module 316 is enabled.

At step 610, system 300 is in type I PLL mode.

CONCLUSION

Although the subject matter has been described in language specific tostructural features and/or methodological acts, it is to be understoodthat the subject matter defined in the appended claims is notnecessarily limited to the specific features or acts described. Rather,the specific features and acts are disclosed as exemplary forms ofimplementing the claims.

1. A method comprising: determining a power state of a power amplifierto receive an output signal of a phase lock loop; enabling the phaselock loop in first mode when the power state of the power amplifier isconstant; and enabling the phase lock loop in second mode when the powerstate of the power amplifier is ramping.
 2. The method of claim 1,wherein enabling the phase lock loop in the first mode includes settingan enable signal of a differentiator to a first state and enabling thephase lock loop in the second mode includes setting the enable signal ofthe differentiator to a second state.
 3. The method of claim 2, whereinenabling the phase lock loop in the first mode includes setting theenable signal of the differentiator module to zero such that adifferentiator module is not enabled.
 4. The method of claim 2, whereinenabling the phase lock loop in the second mode includes setting theenable signal of the differentiator module to logical high such that adifferentiator module is enabled.
 5. The method of claim 2, whereinsetting the enable signal to the first state causes a flip-flop of thedifferentiator to set to a hold state.
 6. The method of claim 2, whereinsetting the enable signal to the second state causes a flip-flop of thedifferentiator to provide an output signal.
 7. The method as recited inclaim 1, further comprising compensating for a feedback signalcomprising a harmonic with the same frequency of an output signal of thephase lock loop, the feedback signal generated by the power amplifier.8. The method as recited in claim 1, further comprising switchingbetween the first mode and the second mode of the phase lock loopwithout generating additional disturbances within the phase lock loop.9. A system comprising: a transceiver module; and a phase lock loopassociated with the transceiver module, the phase lock loop to operatein a first mode when the transceiver module is in a first state and tooperate in a second mode when the transceiver module is in a secondstate.
 10. The system according to claim 9, further comprising a poweramplifier associated with the transceiver module, the power amplifierdetermining the first and second states.
 11. The system according toclaim 10, wherein the first state is to occur when the power amplifieris in a substantially constant state and the second state is to occurwhen the power amplifier is ramping.
 12. The system according to claim9, further comprising a differentiator to enable the phase lock loop tooperate in the first and second modes.
 13. The system according to claim12, wherein the differentiator is to receive an enable signal in a firststate to enable the phase lock loop to operate in the first mode and thedifferentiator is to receive the enable signal in a second state toenable the phase lock loop to operate in the second mode.
 14. The systemaccording to claim 12, wherein the differentiator includes a flip-flop,the flip-flop to receive an enable signal in a first state to enable thephase lock loop to operate in the first mode.
 15. The system accordingto claim 14, wherein the flip-flop is to receive the enable signal in asecond state to enable the phase lock loop to operate in the secondmode.